How to introduce delay in vhdl Videos

• 1. VHDL tutorial: part 02 : Getting started with VHDL
• 2. Asynchronous and Synchronous D flip flop in VHDL
• 3. Writing to port pin and creating delay to blink LED
• 4. Static Hazards
• 5. Constants and Generics [VHDL Recap 3D]
• 6. Verilog Tutorial 10 -- Generate Blocks

VHDL tutorial: part 02 : Getting started with VHDL

Asynchronous and Synchronous D flip flop in VHDL

Writing to port pin and creating delay to blink LED

Static Hazards

User Comments

-Aku mA- commented on 13 Feb 2015

First of all, thank you very much for this video. I finally understand how impulse diagram works. However i'm confused at the diagram for K0. Shouldn't the delay be 1.5 ns and not 2 ns because as you said, "not gates incur half ns propagation". If someone could clarify this to me, i would really appreciate it.

ignas2526 commented on 10 Jan 2012

So what K2 did is removed static hazard, however, the (I0*s') is still needed, so static hazard is compensated in cost of circuitry size. I got this right?

EngMicroLectures commented on 23 Jan 2012

@ignas2526, yes, we can potentially remove the problem of static hazards by strategically increasing the complexity of our circuit.

Maxwell Pietsch commented on 21 Jun 2015

It would be nice to have a link in the description to the previous lecture on which this lecture builds.

louddrummer commented on 02 Mar 2012

to help with the teeth thing, make sure your camera is eye-level... or just tilt your head down.

Niranjan S commented on 04 Jan 2013

Removing static 1 hazard from MUX using non-essential prime-implicants - good idea! Thanks.

chaos1000 commented on 28 Mar 2012

(Thank you)x1billion. Could you upload a lecture on Dynamic Hazards, please.

Sid Nigga commented on 26 Feb 2015

Thank you for that really professional beneficial video. 

danielle4823 commented on 17 Oct 2013

some one please explain why isn't k0 1ns undefined??

John Oliver commented on 13 Mar 2013

Nice! Sharing this with my students @ Cal Poly.

djobele commented on 06 Dec 2012

Thanks, helped a lot

Joonas Nissi commented on 17 Nov 2011

Hide your teeths!

somil shivhare commented on 22 Jan 2015

good work....

Prabhat Pal commented on 03 Dec 2011

good video

Constants and Generics [VHDL Recap 3D]

Verilog Tutorial 10 -- Generate Blocks

User Comments

INDRAJIT GHOSH commented on 24 Feb 2015

does EDA playground wave generator simulate real values ??

Victor Lyuboslavsky commented on 02 Mar 2015

+INDRAJIT GHOSH Yes, it can display real values. Example: //www.edaplayground.com/x/ECV

INDRAJIT GHOSH commented on 02 Mar 2015

+EDA Playground does it displays analog values?

EDA Playground commented on 24 Feb 2015

+INDRAJIT GHOSH Can you elaborate? What do you mean by "real values"?

palli12345 commented on 05 Jan 2015

Can you pls share the code link ? Thanks :-)

EDA Playground commented on 06 Jan 2015

The code links are in the comments above. You have to click SHOW MORE to see them.The generate example from the StackOverflow question: //www.edaplayground.com/s/4/50The generate conditional example from this Verilog tutorial: //www.edaplayground.com/s/example/385

Hayk Dingchyan commented on 13 Nov 2014

First of all thank you for this great video tutorials and user friendly tool. You have covered basics of the Verilog language . Have you plan to create more advance courses ?

Aram Grigoryan commented on 14 Nov 2014

+Hayk Dingchyan chemiche

Hayk Dingchyan commented on 14 Nov 2014

I'm novice but if I will be more professional in Verilog I surely will create tutorials :) 

EDA Playground commented on 13 Nov 2014

We have received requests for additional tutorials. However, if anyone else would like to make some tutorials using EDA Playground, then we can include them on this channel.